OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 207

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
206 partially working exceptions. sybreon 5494d 10h /aemb/trunk/sim/verilog/
191 New directory structure. root 5624d 12h /aemb/trunk/sim/verilog/
164 added random seed sybreon 5907d 17h /aemb/trunk/sim/verilog/
163 updated to new iversim compatibility sybreon 5907d 17h /aemb/trunk/sim/verilog/
157 Added interrupt capability. sybreon 5936d 22h /aemb/trunk/sim/verilog/
143 Fixed minor typos. sybreon 5940d 14h /aemb/trunk/sim/verilog/
138 initial import sybreon 5941d 13h /aemb/trunk/sim/verilog/
98 Minor typo sybreon 6061d 09h /aemb/trunk/sim/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6066d 10h /aemb/trunk/sim/verilog/
92 Partitioned simulation model. sybreon 6071d 12h /aemb/trunk/sim/verilog/
79 Modified for AEMB2 sybreon 6079d 06h /aemb/trunk/sim/verilog/
73 Moved simulation kernel into code. sybreon 6089d 14h /aemb/trunk/sim/verilog/
71 Old version deprecated. sybreon 6096d 17h /aemb/trunk/sim/verilog/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6099d 12h /aemb/trunk/sim/verilog/
67 Minor simulation fixes. sybreon 6101d 11h /aemb/trunk/sim/verilog/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6105d 09h /aemb/trunk/sim/verilog/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6106d 07h /aemb/trunk/sim/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6110d 10h /aemb/trunk/sim/verilog/
50 Parameterised optional components. sybreon 6111d 17h /aemb/trunk/sim/verilog/
49 Added random seed for simulation. sybreon 6114d 20h /aemb/trunk/sim/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.