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[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 208

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Rev Log message Author Age Path
208 removed illegal read/write messages due to misaligned memory exception tests. sybreon 5549d 06h /aemb/trunk/sim/verilog/
206 partially working exceptions. sybreon 5549d 06h /aemb/trunk/sim/verilog/
191 New directory structure. root 5679d 09h /aemb/trunk/sim/verilog/
164 added random seed sybreon 5962d 14h /aemb/trunk/sim/verilog/
163 updated to new iversim compatibility sybreon 5962d 14h /aemb/trunk/sim/verilog/
157 Added interrupt capability. sybreon 5991d 19h /aemb/trunk/sim/verilog/
143 Fixed minor typos. sybreon 5995d 11h /aemb/trunk/sim/verilog/
138 initial import sybreon 5996d 10h /aemb/trunk/sim/verilog/
98 Minor typo sybreon 6116d 06h /aemb/trunk/sim/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6121d 07h /aemb/trunk/sim/verilog/
92 Partitioned simulation model. sybreon 6126d 09h /aemb/trunk/sim/verilog/
79 Modified for AEMB2 sybreon 6134d 03h /aemb/trunk/sim/verilog/
73 Moved simulation kernel into code. sybreon 6144d 11h /aemb/trunk/sim/verilog/
71 Old version deprecated. sybreon 6151d 14h /aemb/trunk/sim/verilog/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6154d 09h /aemb/trunk/sim/verilog/
67 Minor simulation fixes. sybreon 6156d 08h /aemb/trunk/sim/verilog/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6160d 05h /aemb/trunk/sim/verilog/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6161d 04h /aemb/trunk/sim/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6165d 07h /aemb/trunk/sim/verilog/
50 Parameterised optional components. sybreon 6166d 13h /aemb/trunk/sim/verilog/

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