URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 38

Rev	Log message	Author	Age	Path
38	Added interrupt support.	sybreon	6288d 00h	/aemb/trunk/sim/verilog/
31	Removed byte acrobatics.	sybreon	6318d 03h	/aemb/trunk/sim/verilog/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6321d 03h	/aemb/trunk/sim/verilog/
22	Added support for 8-bit and 16-bit data types.	sybreon	6322d 20h	/aemb/trunk/sim/verilog/
19	Added initial unified memory core.	sybreon	6335d 05h	/aemb/trunk/sim/verilog/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6335d 22h	/aemb/trunk/sim/verilog/