URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 58

Rev	Log message	Author	Age	Path
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6085d 20h	/aemb/trunk/sim/verilog/
53	Added GET/PUT support through a FSL bus.	sybreon	6089d 22h	/aemb/trunk/sim/verilog/
50	Parameterised optional components.	sybreon	6091d 05h	/aemb/trunk/sim/verilog/
49	Added random seed for simulation.	sybreon	6094d 08h	/aemb/trunk/sim/verilog/
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6097d 00h	/aemb/trunk/sim/verilog/
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6097d 16h	/aemb/trunk/sim/verilog/
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6108d 00h	/aemb/trunk/sim/verilog/
38	Added interrupt support.	sybreon	6253d 00h	/aemb/trunk/sim/verilog/
31	Removed byte acrobatics.	sybreon	6283d 03h	/aemb/trunk/sim/verilog/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6286d 04h	/aemb/trunk/sim/verilog/
22	Added support for 8-bit and 16-bit data types.	sybreon	6287d 21h	/aemb/trunk/sim/verilog/
19	Added initial unified memory core.	sybreon	6300d 06h	/aemb/trunk/sim/verilog/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6300d 23h	/aemb/trunk/sim/verilog/