OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] - Rev 20

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.
csantifort 4851d 22h /amber/
19 Create a configuration log file as part of the synthesis flow. This file is a useful reference to
tell the different bitfiles apart.
csantifort 4851d 22h /amber/
18 Added list of source files and diagram for Amber25 core. csantifort 4854d 21h /amber/
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions
csantifort 4855d 20h /amber/
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.
csantifort 4858d 10h /amber/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 4858d 10h /amber/
14 Re-wrote the behavioral clock generation code to more accurately
calculate the sys_clk frequency. The previous version was not
producing the correct frequency at higher frequenies due to
rounding errors.
csantifort 4859d 22h /amber/
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.
csantifort 4859d 22h /amber/
12 Added INITIALIZE_TO_ZERO parameter to keep instantiation
idendical to generic sram models. The parameter is not used
in the Xilinx models (they always init to zero) but it used
in the generic models.
csantifort 4859d 22h /amber/
11 Added vmlinux test. csantifort 4874d 22h /amber/
10 Removed parameters for unused peruipheral modules csantifort 4876d 02h /amber/
9 Change the format of mcr and mrc listings so they exactly match the dissasembly produced by the gnu tools.
Write ip instead of r12 in listings.
csantifort 4876d 02h /amber/
8 Change the value in the ID register to be compatible with the Linux code that parses it and picks a processor type. csantifort 4876d 02h /amber/
7 Added instructions to use Veritak simulator.
Removed some unused functions from memory_configuration.v.
csantifort 4884d 17h /amber/
6 Set ignore property for output files csantifort 4887d 20h /amber/
5 Deleted two temporary files that should not be in the release. csantifort 4888d 16h /amber/
4 Corrected a couple of minor typos csantifort 4888d 16h /amber/
3 Added trunk to $AMBER_BASE path csantifort 4888d 20h /amber/
2 Baseline release of the Amber 2 core csantifort 4888d 20h /amber/
1 The project and the structure was created root 4915d 23h /amber/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.