OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] - Rev 57

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
57 Add some debug messages csantifort 4693d 15h /amber/
56 Remove the timeouts file from svn. Its an output file and gets now just gets created automatically
when sims are run for the first time.
csantifort 4693d 15h /amber/
55 Added sudo to rm mnt command csantifort 4693d 15h /amber/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.
csantifort 4710d 15h /amber/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4725d 12h /amber/
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4725d 13h /amber/
51 Revert vmlinux back to 48. csantifort 4766d 12h /amber/
50 Revert to previous version csantifort 4766d 12h /amber/
49 Added a note n how to change timeouts csantifort 4766d 13h /amber/
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.
csantifort 4770d 19h /amber/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4790d 16h /amber/
46 svn ignore vmlinux.dis and vmlinux.mem csantifort 4798d 14h /amber/
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4798d 14h /amber/
44 Updated vmlinux image based on last change csantifort 4798d 15h /amber/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 4798d 15h /amber/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4816d 11h /amber/
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4817d 20h /amber/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 4822d 12h /amber/
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly
csantifort 4823d 13h /amber/
38 support 128-bit wishbone now used for a25 core csantifort 4824d 13h /amber/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.