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[/] [amber/] [trunk/] - Rev 31

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Rev Log message Author Age Path
31 Added dhrystone benchmark test csantifort 4824d 11h /amber/trunk/
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 4837d 18h /amber/trunk/
29 Use lgo command for saving waveforms in modelsim csantifort 4839d 11h /amber/trunk/
28 Moved function prototypes to .h file csantifort 4839d 12h /amber/trunk/
27 Got working with cadence nc simulator csantifort 4872d 19h /amber/trunk/
26 Added wish list csantifort 4877d 19h /amber/trunk/
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh
csantifort 4879d 16h /amber/trunk/
24 Added instructions how to build Linux kernel from source files csantifort 4881d 16h /amber/trunk/
23 Split the source files list into a Vertex-6 only list and a Spartan-6 only list.
That way users don;t need to delete files from the list manually if they only have
a setup for one of the FPGA types.
csantifort 4881d 17h /amber/trunk/
22 Added files and instructions to enable the building of the vmlinux image from the kernel source files. csantifort 4885d 16h /amber/trunk/
21 Fixed bug in the conditions to create the FPGA configuration log file. I added the creation of the log file in the last release, but the way it was implemented was causing the Makefile to always rebuild from the start. csantifort 4885d 16h /amber/trunk/
20 Added feature to A25 core to directly use a read value from the write back stage
to reduce the stall to 1 cycle when there is a register conflict with the
following instruction. This increases performance by about 3%.
csantifort 4906d 17h /amber/trunk/
19 Create a configuration log file as part of the synthesis flow. This file is a useful reference to
tell the different bitfiles apart.
csantifort 4906d 18h /amber/trunk/
18 Added list of source files and diagram for Amber25 core. csantifort 4909d 16h /amber/trunk/
17 amber25 core bug fix. The return address for irq interrupts was off by 4 bytes
when the interrupt occurred during a stm instruction with the following instruction
having some register conflicts. Added test irq_stm to catch the bug.
Cleaned up some header descriptions
csantifort 4910d 15h /amber/trunk/
16 Deleted the old version of the 3-state amber core. Its replaced with amber23.
Added the 5-state Amber core.
csantifort 4913d 06h /amber/trunk/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 4913d 06h /amber/trunk/
14 Re-wrote the behavioral clock generation code to more accurately
calculate the sys_clk frequency. The previous version was not
producing the correct frequency at higher frequenies due to
rounding errors.
csantifort 4914d 18h /amber/trunk/
13 Bug fix - added an extra state to the rx state machine to properly align
reading the uart input to the middle of each bit.
csantifort 4914d 18h /amber/trunk/
12 Added INITIALIZE_TO_ZERO parameter to keep instantiation
idendical to generic sram models. The parameter is not used
in the Xilinx models (they always init to zero) but it used
in the generic models.
csantifort 4914d 18h /amber/trunk/

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