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[/] [amber/] [trunk/] [hw/] - Rev 50

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Rev Log message Author Age Path
50 Revert to previous version csantifort 4706d 18h /amber/trunk/hw/
49 Added a note n how to change timeouts csantifort 4706d 18h /amber/trunk/hw/
48 Fixed a bug in linux that caused the os to not return to the running application after an interrupt.
Hello-world now runs stand-alone again.
Added initrd-200k-dhry, a disk image that uses the dhry program for init.
csantifort 4711d 01h /amber/trunk/hw/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4730d 22h /amber/trunk/hw/
45 Store vmlinux.mem and vmlinux.dis in compressed form csantifort 4738d 20h /amber/trunk/hw/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.
csantifort 4738d 20h /amber/trunk/hw/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4756d 17h /amber/trunk/hw/
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4758d 01h /amber/trunk/hw/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.
csantifort 4762d 18h /amber/trunk/hw/
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly
csantifort 4763d 19h /amber/trunk/hw/
38 support 128-bit wishbone now used for a25 core csantifort 4764d 19h /amber/trunk/hw/
37 128-bit wide boot memory module csantifort 4765d 17h /amber/trunk/hw/
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4765d 18h /amber/trunk/hw/
35 Amber25 improvements:
Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times
Use a fast barrel shifter for shifts between 0 and 4 to improve timing
Use a 2 cycle full barrel shifter for complex shifts
csantifort 4767d 01h /amber/trunk/hw/
32 Added clock cycle counting register to test_module to support dhrystone performance measurement csantifort 4769d 18h /amber/trunk/hw/
30 Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays csantifort 4783d 01h /amber/trunk/hw/
29 Use lgo command for saving waveforms in modelsim csantifort 4784d 19h /amber/trunk/hw/
27 Got working with cadence nc simulator csantifort 4818d 02h /amber/trunk/hw/
25 Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size.
Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again.
Tidy up: Removed a debug message from hw/tools/run.sh
csantifort 4824d 23h /amber/trunk/hw/
23 Split the source files list into a Vertex-6 only list and a Spartan-6 only list.
That way users don;t need to delete files from the list manually if they only have
a setup for one of the FPGA types.
csantifort 4827d 01h /amber/trunk/hw/

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