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[/] [amber/] [trunk/] [hw/] - Rev 73

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Rev	Log message	Author	Age	Path
73	The patch introduces a new configuration option `A23_RAM_REGISTER_BANK, which controls instantiation of Amber 23 register bank. If the option is set, a ram-based variant of the register bank is instantiated. It can be useful in low-end FPGA designs, where flipflops and muxes are costly. Altera Cyclone III resource utilization: - flipflop-based register bank: 1583 combinationals + 856 registers - ram-based register bank: 268 combinationals + 156 registers Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4059d 01h	/amber/trunk/hw/
72	5 bit "OH_USR" constant was used when 2 bit "USR" should be used. Both of the constants are 0. The fault was introduced by ram-based register bank commit. Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4059d 01h	/amber/trunk/hw/
71	Original Amber 23 core uses asyncronous implementation of register bank. It leads to some problems with ram-based implementation of the register bank, because at least Altera FPGAs uses syncronous ram blocks, so the whole address needs to be latched. The patch exposes non-registered versions of register select signals to the register bank, so the bank can build address and latch it in the syncronous ram input register. The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA. Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4059d 01h	/amber/trunk/hw/
70	The mlas_bug testcase tried to use stack without setting stack pointer register, causing unpredictable behavoiur. The patch uses an expilict stack area for the test. Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>	csantifort	4059d 01h	/amber/trunk/hw/
68	Remove modelsim files. Only supporting Xilinx isim now.	csantifort	4059d 02h	/amber/trunk/hw/
67	renamed boot-loader.c to boot-loader-serial.c	csantifort	4059d 02h	/amber/trunk/hw/
64	Support latest Xilinx ISE 14.5 software.	csantifort	4059d 03h	/amber/trunk/hw/
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4059d 07h	/amber/trunk/hw/
61	Add new netowkr based boot loader. Remove support for Virtex. Spartan 6 only now.	csantifort	4346d 02h	/amber/trunk/hw/
60	Bug fix; removed a combinational loop from the a25_decode logic.	csantifort	4563d 22h	/amber/trunk/hw/
59	Added modelsim script for reloading a wlf file after a simulation has been rerun.	csantifort	4633d 19h	/amber/trunk/hw/
58	Use TB.clk_count for the decompiler messages and removed the local counter	csantifort	4633d 23h	/amber/trunk/hw/
57	Add some debug messages	csantifort	4633d 23h	/amber/trunk/hw/
56	Remove the timeouts file from svn. Its an output file and gets now just gets created automatically when sims are run for the first time.	csantifort	4633d 23h	/amber/trunk/hw/
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4650d 23h	/amber/trunk/hw/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4665d 21h	/amber/trunk/hw/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4665d 21h	/amber/trunk/hw/
50	Revert to previous version	csantifort	4706d 20h	/amber/trunk/hw/
49	Added a note n how to change timeouts	csantifort	4706d 21h	/amber/trunk/hw/
48	Fixed a bug in linux that caused the os to not return to the running application after an interrupt. Hello-world now runs stand-alone again. Added initrd-200k-dhry, a disk image that uses the dhry program for init.	csantifort	4711d 03h	/amber/trunk/hw/

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[/] [amber/] [trunk/] [hw/] - Rev 73

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