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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 54

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Rev	Log message	Author	Age	Path
54	Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers was selected for writing to for 1 clock cycle.	csantifort	4768d 05h	/amber/trunk/hw/vlog/
53	Cleaned up Amber Verilog, removing unused signals.	csantifort	4783d 02h	/amber/trunk/hw/vlog/
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4783d 02h	/amber/trunk/hw/vlog/
49	Added a note n how to change timeouts	csantifort	4824d 02h	/amber/trunk/hw/vlog/
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	4848d 06h	/amber/trunk/hw/vlog/
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	4856d 05h	/amber/trunk/hw/vlog/
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	4874d 01h	/amber/trunk/hw/vlog/
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	4875d 10h	/amber/trunk/hw/vlog/
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	4880d 02h	/amber/trunk/hw/vlog/
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	4881d 03h	/amber/trunk/hw/vlog/
38	support 128-bit wishbone now used for a25 core	csantifort	4882d 03h	/amber/trunk/hw/vlog/
37	128-bit wide boot memory module	csantifort	4883d 01h	/amber/trunk/hw/vlog/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	4883d 02h	/amber/trunk/hw/vlog/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4884d 09h	/amber/trunk/hw/vlog/
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	4887d 02h	/amber/trunk/hw/vlog/
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	4900d 09h	/amber/trunk/hw/vlog/
27	Got working with cadence nc simulator	csantifort	4935d 10h	/amber/trunk/hw/vlog/
20	Added feature to A25 core to directly use a read value from the write back stage to reduce the stall to 1 cycle when there is a register conflict with the following instruction. This increases performance by about 3%.	csantifort	4969d 09h	/amber/trunk/hw/vlog/
17	amber25 core bug fix. The return address for irq interrupts was off by 4 bytes when the interrupt occurred during a stm instruction with the following instruction having some register conflicts. Added test irq_stm to catch the bug. Cleaned up some header descriptions	csantifort	4973d 07h	/amber/trunk/hw/vlog/
16	Deleted the old version of the 3-state amber core. Its replaced with amber23. Added the 5-state Amber core.	csantifort	4975d 21h	/amber/trunk/hw/vlog/

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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 54

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