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[/] [amber/] [trunk/] [hw/] [vlog/] - Rev 71

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71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4062d 02h /amber/trunk/hw/vlog/
64 Support latest Xilinx ISE 14.5 software. csantifort 4062d 03h /amber/trunk/hw/vlog/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4062d 08h /amber/trunk/hw/vlog/
61 Add new netowkr based boot loader.
Remove support for Virtex. Spartan 6 only now.		 csantifort 4349d 02h /amber/trunk/hw/vlog/
60 Bug fix; removed a combinational loop from the a25_decode logic. csantifort 4566d 22h /amber/trunk/hw/vlog/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4636d 23h /amber/trunk/hw/vlog/
57 Add some debug messages csantifort 4636d 23h /amber/trunk/hw/vlog/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4653d 23h /amber/trunk/hw/vlog/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4668d 21h /amber/trunk/hw/vlog/
52 Fixed typo in notes on creating DDR memory interfaces using coregen csantifort 4668d 21h /amber/trunk/hw/vlog/
49 Added a note n how to change timeouts csantifort 4709d 21h /amber/trunk/hw/vlog/
47 Changed V6 VCo from 1000Mhz to 1200 MHz csantifort 4734d 01h /amber/trunk/hw/vlog/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 4741d 23h /amber/trunk/hw/vlog/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4759d 19h /amber/trunk/hw/vlog/
41 Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface. csantifort 4761d 04h /amber/trunk/hw/vlog/
40 Added wishbone bus jitter testing option.
Cleaned up waveform log .do files, now seperate files for a23 and a25 cores.
Added vmlinux executable elf file for running on hardware.		 csantifort 4765d 20h /amber/trunk/hw/vlog/
39 Added a second level of buffering to a25_wishbone_buf to fix a lockup
bug when write acks to not return immediately, and also to improve performance slightly		 csantifort 4766d 21h /amber/trunk/hw/vlog/
38 support 128-bit wishbone now used for a25 core csantifort 4767d 21h /amber/trunk/hw/vlog/
37 128-bit wide boot memory module csantifort 4768d 19h /amber/trunk/hw/vlog/
36 Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus csantifort 4768d 20h /amber/trunk/hw/vlog/

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