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[/] [amber/] [trunk/] [hw/] [vlog/] [amber23/] - Rev 75

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74 The patch implements barrel shifter using rotate as a main primitive.
The design was optimized for Altera Cyclone III FPGA and can be reused
with other FPGA vendors and products.
The patch integrates the FPGA-optimized barrel shifter into the
Amber 23 core when it is build for Altera FPGA.

The patch reduces footprint from 1178 to 339 LEs keeping Fmax at 57-60 MHz.

Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4214d 01h /amber/trunk/hw/vlog/amber23/
73 The patch introduces a new configuration option `A23_RAM_REGISTER_BANK,
which controls instantiation of Amber 23 register bank.
If the option is set, a ram-based variant of the register bank is instantiated.
It can be useful in low-end FPGA designs, where flipflops and muxes are costly.

Altera Cyclone III resource utilization:
- flipflop-based register bank: 1583 combinationals + 856 registers
- ram-based register bank: 268 combinationals + 156 registers

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4214d 01h /amber/trunk/hw/vlog/amber23/
72 5 bit "OH_USR" constant was used when 2 bit "USR" should be used.
Both of the constants are 0.
The fault was introduced by ram-based register bank commit.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4214d 02h /amber/trunk/hw/vlog/amber23/
71 Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.

The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.

The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.

Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>		 csantifort 4214d 02h /amber/trunk/hw/vlog/amber23/
63 Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files.		 csantifort 4214d 08h /amber/trunk/hw/vlog/amber23/
58 Use TB.clk_count for the decompiler messages and removed the local counter csantifort 4788d 23h /amber/trunk/hw/vlog/amber23/
54 Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle.		 csantifort 4805d 23h /amber/trunk/hw/vlog/amber23/
53 Cleaned up Amber Verilog, removing unused signals. csantifort 4820d 21h /amber/trunk/hw/vlog/amber23/
43 Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.		 csantifort 4893d 23h /amber/trunk/hw/vlog/amber23/
42 Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete csantifort 4911d 19h /amber/trunk/hw/vlog/amber23/
15 Copied amber to amber23, Many system changes to support new amber25 core. csantifort 5013d 15h /amber/trunk/hw/vlog/amber23/
2 Baseline release of the Amber 2 core csantifort 5044d 02h /amber/trunk/hw/vlog/amber/

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