URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [tb/] - Rev 37

Rev	Log message	Author	Age	Path
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	4928d 23h	/amber/trunk/hw/vlog/tb/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4930d 06h	/amber/trunk/hw/vlog/tb/
27	Got working with cadence nc simulator	csantifort	4981d 07h	/amber/trunk/hw/vlog/tb/
17	amber25 core bug fix. The return address for irq interrupts was off by 4 bytes when the interrupt occurred during a stm instruction with the following instruction having some register conflicts. Added test irq_stm to catch the bug. Cleaned up some header descriptions	csantifort	5019d 04h	/amber/trunk/hw/vlog/tb/
15	Copied amber to amber23, Many system changes to support new amber25 core.	csantifort	5021d 18h	/amber/trunk/hw/vlog/tb/
11	Added vmlinux test.	csantifort	5038d 06h	/amber/trunk/hw/vlog/tb/
2	Baseline release of the Amber 2 core	csantifort	5052d 04h	/amber/trunk/hw/vlog/tb/