URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [tb/] - Rev 78

Rev	Log message	Author	Age	Path
63	Add support for Xilinx ISim Verilog simulator. Remove Virtex-6 files.	csantifort	4146d 04h	/amber/trunk/hw/vlog/tb/
61	Add new netowkr based boot loader. Remove support for Virtex. Spartan 6 only now.	csantifort	4432d 23h	/amber/trunk/hw/vlog/tb/
49	Added a note n how to change timeouts	csantifort	4793d 17h	/amber/trunk/hw/vlog/tb/
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	4852d 17h	/amber/trunk/hw/vlog/tb/
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4854d 00h	/amber/trunk/hw/vlog/tb/
27	Got working with cadence nc simulator	csantifort	4905d 01h	/amber/trunk/hw/vlog/tb/
17	amber25 core bug fix. The return address for irq interrupts was off by 4 bytes when the interrupt occurred during a stm instruction with the following instruction having some register conflicts. Added test irq_stm to catch the bug. Cleaned up some header descriptions	csantifort	4942d 22h	/amber/trunk/hw/vlog/tb/
15	Copied amber to amber23, Many system changes to support new amber25 core.	csantifort	4945d 12h	/amber/trunk/hw/vlog/tb/
11	Added vmlinux test.	csantifort	4962d 00h	/amber/trunk/hw/vlog/tb/
2	Baseline release of the Amber 2 core	csantifort	4975d 22h	/amber/trunk/hw/vlog/tb/