URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] - Rev 22

Rev	Log message	Author	Age	Path
22	roll back	wsong0210	4761d 00h	/async_sdm_noc/
21	prepare trunk	wsong0210	4761d 00h	/async_sdm_noc/
20	prepare trunk	wsong0210	4761d 00h	/async_sdm_noc/
19	sdm router ready	wsong0210	4761d 05h	/async_sdm_noc/
18	allocators_modify	wsong0210	4762d 05h	/async_sdm_noc/
17	allocators	wsong0210	4762d 05h	/async_sdm_noc/
16	input buffers	wsong0210	4762d 06h	/async_sdm_noc/
15	update license	wsong0210	4763d 01h	/async_sdm_noc/
14	output buffers	wsong0210	4763d 04h	/async_sdm_noc/
13	router structure configuration	wsong0210	4763d 05h	/async_sdm_noc/
12	crossbars	wsong0210	4763d 05h	/async_sdm_noc/
11	arbiters	wsong0210	4763d 06h	/async_sdm_noc/
10	script for async cell lib disable timing arc	wsong0210	4765d 08h	/async_sdm_noc/
9	cell library setting up script	wsong0210	4765d 22h	/async_sdm_noc/
8	update the async cell lib	wsong0210	4765d 23h	/async_sdm_noc/
7	add the verilog Nangate simulation file	wsong0210	4765d 23h	/async_sdm_noc/
6	the asynchronous cell library	wsong0210	4766d 00h	/async_sdm_noc/
5	modify the file dir for multiple designs	wsong0210	4766d 00h	/async_sdm_noc/
4	update license and cell lib	wsong0210	4766d 05h	/async_sdm_noc/
3	directories	wsong0210	4776d 22h	/async_sdm_noc/