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[/] [ata/] [trunk/] - Rev 18

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Rev Log message Author Age Path
18 Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high. rherveille 8312d 09h /ata/trunk/
17 Changed top-level. Made asynchronous reset programmable. rherveille 8318d 06h /ata/trunk/
16 - Added Test Bench
- Added Synthesis scripts for Design Compiler
- Fixed minor bug in atahost_top		 rudi 8345d 05h /ata/trunk/
15 Changed filenames and top-level port names to be conform new OpenCores conventions rherveille 8346d 03h /ata/trunk/
14 created new directory structure rherveille 8358d 04h /ata/trunk/
13 no message rherveille 8358d 04h /ata/trunk/
12 Fixed some blocking versus non-blocking statement issues. rherveille 8365d 09h /ata/trunk/
11 Created directory structure (documentation, vhdl, verilog) rherveille 8375d 22h /ata/trunk/
10 - renamed 'ata.vhd' to 'atahost.vhd'
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).		 rherveille 8380d 23h /ata/trunk/
9 - renamed 'ata.vhd' to 'atahost.vhd'
- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).		 rherveille 8380d 23h /ata/trunk/
8 Fixed sensitivity error in ata.v (nRESET instead of nReset) rherveille 8381d 09h /ata/trunk/
7 no message rherveille 8382d 20h /ata/trunk/
6 Added 'timescale to all files
Fixed bug where control registers would always latch data, instead of when addressed		 rherveille 8382d 20h /ata/trunk/
5 Rewrote some sections. Minor Verilog coding style issues. rherveille 8389d 01h /ata/trunk/
4 Fixed some incomplete port lists. Fixed some Verilog related issues.
Design now compiles completely.		 rherveille 8390d 06h /ata/trunk/
3 Created VHDL & Verilog subdirectories. Moved files accordingly. rherveille 8393d 00h /ata/trunk/
2 Initial verilog release rherveille 8393d 01h /ata/trunk/
1 Standard project directories initialized by cvs2svn. 8393d 01h /ata/trunk/

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