URL https://opencores.org/ocsvn/ata/ata/trunk

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[/] [ata/] [trunk/] - Rev 22

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Rev	Log message	Author	Age	Path
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8182d 05h	/ata/trunk/
21	Changed atahost_top pin-information.	rherveille	8182d 05h	/ata/trunk/
20	Some minor bug fixes	rherveille	8296d 01h	/ata/trunk/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8305d 07h	/ata/trunk/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8333d 10h	/ata/trunk/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8339d 07h	/ata/trunk/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8366d 06h	/ata/trunk/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8367d 04h	/ata/trunk/
14	created new directory structure	rherveille	8379d 06h	/ata/trunk/
13	no message	rherveille	8379d 06h	/ata/trunk/
12	Fixed some blocking versus non-blocking statement issues.	rherveille	8386d 11h	/ata/trunk/
11	Created directory structure (documentation, vhdl, verilog)	rherveille	8396d 23h	/ata/trunk/
10	- renamed 'ata.vhd' to 'atahost.vhd' - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8402d 01h	/ata/trunk/
9	- renamed 'ata.vhd' to 'atahost.vhd' - Changed PIOreq & PIOack generation (controller.vhd); made them synchronous - Changed 'go' & 'igo' generation (pio_tctrl.vhdl).	rherveille	8402d 01h	/ata/trunk/
8	Fixed sensitivity error in ata.v (nRESET instead of nReset)	rherveille	8402d 11h	/ata/trunk/
7	no message	rherveille	8403d 21h	/ata/trunk/
6	Added 'timescale to all files Fixed bug where control registers would always latch data, instead of when addressed	rherveille	8403d 21h	/ata/trunk/
5	Rewrote some sections. Minor Verilog coding style issues.	rherveille	8410d 02h	/ata/trunk/
4	Fixed some incomplete port lists. Fixed some Verilog related issues. Design now compiles completely.	rherveille	8411d 07h	/ata/trunk/
3	Created VHDL & Verilog subdirectories. Moved files accordingly.	rherveille	8414d 02h	/ata/trunk/

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[/] [ata/] [trunk/] - Rev 22

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