URL https://opencores.org/ocsvn/ata/ata/trunk

Subversion Repositories ata

[/] [ata/] [trunk/] - Rev 8

Rev	Log message	Author	Age	Path
8	Fixed sensitivity error in ata.v (nRESET instead of nReset)	rherveille	8362d 17h	/ata/trunk/
7	no message	rherveille	8364d 04h	/ata/trunk/
6	Added 'timescale to all files Fixed bug where control registers would always latch data, instead of when addressed	rherveille	8364d 04h	/ata/trunk/
5	Rewrote some sections. Minor Verilog coding style issues.	rherveille	8370d 09h	/ata/trunk/
4	Fixed some incomplete port lists. Fixed some Verilog related issues. Design now compiles completely.	rherveille	8371d 13h	/ata/trunk/
3	Created VHDL & Verilog subdirectories. Moved files accordingly.	rherveille	8374d 08h	/ata/trunk/
2	Initial verilog release	rherveille	8374d 08h	/ata/trunk/
1	Standard project directories initialized by cvs2svn.		8374d 08h	/ata/trunk/