URL https://opencores.org/ocsvn/ata/ata/trunk

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[/] [ata/] [trunk/] [rtl/] [verilog/] - Rev 19

Rev	Log message	Author	Age	Path
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8279d 10h	/ata/trunk/rtl/verilog/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8307d 14h	/ata/trunk/rtl/verilog/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8313d 11h	/ata/trunk/rtl/verilog/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8340d 09h	/ata/trunk/rtl/verilog/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8341d 08h	/ata/trunk/rtl/verilog/
14	created new directory structure	rherveille	8353d 09h	/ata/trunk/rtl/verilog/