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[/] [ata/] [trunk/] [rtl/] [verilog/] [ocidec-1/] - Rev 33

Rev	Log message	Author	Age	Path
33	New directory structure.	root	5566d 15h	/ata/trunk/rtl/verilog/ocidec-1/
32	Fixed a potential bug where the core was forced into an unknown state when an asynchronous reset was given without a running clock.	rherveille	8053d 04h	/ata/trunk/rtl/verilog/ocidec-1/
23	Moved wishbone interface into 'atahost_wb_slave.v' Major revisions in all cores.	rherveille	8142d 19h	/ata/trunk/rtl/verilog/ocidec-1/
22	Added disclaimer Added CVS information Changed core for new internal counter libraries (synthesis fixes).	rherveille	8144d 23h	/ata/trunk/rtl/verilog/ocidec-1/
19	Changed RST_LVL define to parameter. Removed atahost_define.v	rherveille	8268d 01h	/ata/trunk/rtl/verilog/ocidec-1/
18	Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.	rherveille	8296d 04h	/ata/trunk/rtl/verilog/ocidec-1/
17	Changed top-level. Made asynchronous reset programmable.	rherveille	8302d 01h	/ata/trunk/rtl/verilog/ocidec-1/
16	- Added Test Bench - Added Synthesis scripts for Design Compiler - Fixed minor bug in atahost_top	rudi	8329d 00h	/ata/trunk/rtl/verilog/ocidec-1/
15	Changed filenames and top-level port names to be conform new OpenCores conventions	rherveille	8329d 22h	/ata/trunk/rtl/verilog/ocidec-1/
14	created new directory structure	rherveille	8341d 23h	/ata/trunk/rtl/verilog/ocidec-1/