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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec2/] - Rev 31

Rev	Log message	Author	Age	Path
31	Changed internal counter libraries. Split counter.vhd into separate files. Core is in same state as Verilog version now.	rherveille	8204d 01h	/ata/trunk/rtl/vhdl/ocidec2/
26	renamed 'atahost.vhd' to 'atahost_top.vhd' renamed 'controller.vhd' to 'atahost_controller.vhd' renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd'	rherveille	8214d 14h	/ata/trunk/rtl/vhdl/ocidec2/
14	created new directory structure	rherveille	8413d 18h	/ata/trunk/rtl/vhdl/ocidec2/