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[/] [ata/] [trunk/] [rtl/] [vhdl/] [ocidec3/] - Rev 33

Rev	Log message	Author	Age	Path
33	New directory structure.	root	5567d 03h	/ata/trunk/rtl/vhdl/ocidec3/
31	Changed internal counter libraries. Split counter.vhd into separate files. Core is in same state as Verilog version now.	rherveille	8132d 18h	/ata/trunk/rtl/vhdl/ocidec3/
27	renamed all files to 'atahost_***.vhd' broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd' changed resD input to generic RESD in ud_cnt.vhd changed ID input to generic ID in ro_cnt.vhd changed core to reflect changes in ro_cnt.vhd removed references to 'count' library changed IO names added disclaimer added CVS log moved registers and wishbone signals into 'atahost_wb_slave.vhd'	rherveille	8143d 07h	/ata/trunk/rtl/vhdl/ocidec3/
20	Some minor bug fixes	rherveille	8259d 07h	/ata/trunk/rtl/vhdl/ocidec3/
14	created new directory structure	rherveille	8342d 11h	/ata/trunk/rtl/vhdl/ocidec3/