OpenCores
URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] - Rev 14

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 4030d 02h /axi4_tlm_bfm/
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 4030d 06h /axi4_tlm_bfm/
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 4039d 10h /axi4_tlm_bfm/
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 4041d 05h /axi4_tlm_bfm/
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 4045d 05h /axi4_tlm_bfm/
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 4048d 01h /axi4_tlm_bfm/
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4148d 07h /axi4_tlm_bfm/
7 [minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). daniel.kho 4152d 01h /axi4_tlm_bfm/
6 [minor]: expanded some waveforms and show random stimulus from simulation script. daniel.kho 4152d 06h /axi4_tlm_bfm/
5 [minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'. daniel.kho 4152d 10h /axi4_tlm_bfm/
4 [minor]: Removed unused libraries from simulation script. daniel.kho 4153d 04h /axi4_tlm_bfm/
3 Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow. daniel.kho 4153d 05h /axi4_tlm_bfm/
2 Initial commit.
Added packages and usage example for AXI4-Stream protocol.
Added simulation scripts for ModelSim/QuestaSim.		 daniel.kho 4153d 14h /axi4_tlm_bfm/
1 The project and the structure was created root 4154d 01h /axi4_tlm_bfm/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.