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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] - Rev 44

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Rev Log message Author Age Path
44 Committed latest changes to Quartus synthesis folder and some minor changes. daniel.kho 3515d 20h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
42 Major enhancements and bugfix. Used DDR for AXI BFM for enhanced functionality and performance. Tested in simulation; TODO update synthesis design files. daniel.kho 3860d 20h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
25 Refactored folders. daniel.kho 3938d 02h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
23 Added top-level user example used in technical paper. daniel.kho 3945d 20h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3948d 23h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3948d 23h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 4051d 19h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
15 [minor]: cleaned up sources. daniel.kho 4054d 02h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 4062d 16h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 4062d 21h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 4072d 01h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 4073d 19h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 4080d 16h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/

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