URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] - Rev 16

Rev	Log message	Author	Age	Path
16	Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input.	daniel.kho	4005d 01h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
15	[minor]: cleaned up sources.	daniel.kho	4007d 07h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
14	Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap.	daniel.kho	4015d 22h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
13	Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well.	daniel.kho	4016d 02h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
12	Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources.	daniel.kho	4025d 07h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
11	Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match.	daniel.kho	4027d 01h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/
9	Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages.	daniel.kho	4033d 21h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/