URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [workspace/] - Rev 26

Rev	Log message	Author	Age	Path
26	Refactored simulation folders.	daniel.kho	3790d 06h	/axi4_tlm_bfm/trunk/workspace/
24	Updated simulation sources to reflect changes made for synthesis.	daniel.kho	3790d 07h	/axi4_tlm_bfm/trunk/workspace/
22	Added pin assignments for BeMicro kit. Added demo top-level used in technical paper.	daniel.kho	3798d 00h	/axi4_tlm_bfm/trunk/workspace/
19	Updated synthesis constraints and scripts.	daniel.kho	3801d 03h	/axi4_tlm_bfm/trunk/workspace/
16	Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input.	daniel.kho	3903d 23h	/axi4_tlm_bfm/trunk/workspace/
15	[minor]: cleaned up sources.	daniel.kho	3906d 06h	/axi4_tlm_bfm/trunk/workspace/
14	Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap.	daniel.kho	3914d 20h	/axi4_tlm_bfm/trunk/workspace/
13	Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well.	daniel.kho	3915d 01h	/axi4_tlm_bfm/trunk/workspace/
11	Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match.	daniel.kho	3925d 23h	/axi4_tlm_bfm/trunk/workspace/
9	Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages.	daniel.kho	3932d 20h	/axi4_tlm_bfm/trunk/workspace/