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[/] [axi4_tlm_bfm/] [trunk/] [workspace/] - Rev 31

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Rev Log message Author Age Path
31 Added initial Xilinx Vivado synthesis scripts and constraints. daniel.kho 3805d 10h /axi4_tlm_bfm/trunk/workspace/
30 Refactored synthesis scripts. daniel.kho 3805d 10h /axi4_tlm_bfm/trunk/workspace/
29 Updated simulation scripts. daniel.kho 3805d 10h /axi4_tlm_bfm/trunk/workspace/
28 Temporarily remove simulation folder. daniel.kho 3805d 10h /axi4_tlm_bfm/trunk/workspace/
27 Updated simulation scripts. daniel.kho 3805d 10h /axi4_tlm_bfm/trunk/workspace/
26 Refactored simulation folders. daniel.kho 3805d 10h /axi4_tlm_bfm/trunk/workspace/
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3805d 11h /axi4_tlm_bfm/trunk/workspace/
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3813d 05h /axi4_tlm_bfm/trunk/workspace/
19 Updated synthesis constraints and scripts. daniel.kho 3816d 07h /axi4_tlm_bfm/trunk/workspace/
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3919d 04h /axi4_tlm_bfm/trunk/workspace/
15 [minor]: cleaned up sources. daniel.kho 3921d 11h /axi4_tlm_bfm/trunk/workspace/
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3930d 01h /axi4_tlm_bfm/trunk/workspace/
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3930d 05h /axi4_tlm_bfm/trunk/workspace/
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3941d 04h /axi4_tlm_bfm/trunk/workspace/
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3948d 00h /axi4_tlm_bfm/trunk/workspace/

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