URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] - Rev 10

Rev	Log message	Author	Age	Path
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4489d 18h	/bustap-jtag/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4490d 12h	/bustap-jtag/
8	Added fault handling of wrong input length in the GUI.	ash_riple	4494d 12h	/bustap-jtag/
7	Added references related to "Bus Monitor".	ash_riple	4494d 16h	/bustap-jtag/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4495d 12h	/bustap-jtag/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4498d 13h	/bustap-jtag/
4	Created tag for original source code. Version 1.0.	ash_riple	4498d 16h	/bustap-jtag/
3	Added original article.	ash_riple	4498d 16h	/bustap-jtag/
2	Checked in working code base.	ash_riple	4502d 12h	/bustap-jtag/
1	The project and the structure was created	root	4503d 02h	/bustap-jtag/