URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] - Rev 12

Rev	Log message	Author	Age	Path
12	Added timing information to the capture content.	ash_riple	4468d 06h	/bustap-jtag/
11	Added pre-trigger capture.	ash_riple	4468d 21h	/bustap-jtag/
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4474d 02h	/bustap-jtag/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4474d 21h	/bustap-jtag/
8	Added fault handling of wrong input length in the GUI.	ash_riple	4478d 21h	/bustap-jtag/
7	Added references related to "Bus Monitor".	ash_riple	4479d 01h	/bustap-jtag/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4479d 21h	/bustap-jtag/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4482d 22h	/bustap-jtag/
4	Created tag for original source code. Version 1.0.	ash_riple	4483d 00h	/bustap-jtag/
3	Added original article.	ash_riple	4483d 01h	/bustap-jtag/
2	Checked in working code base.	ash_riple	4486d 21h	/bustap-jtag/
1	The project and the structure was created	root	4487d 11h	/bustap-jtag/