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[/] [bustap-jtag/] - Rev 23

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Rev Log message Author Age Path
23 Updated Altera Tcl script to 32bit address bus. ash_riple 3858d 03h /bustap-jtag/
22 ash_riple 3858d 08h /bustap-jtag/
21 ash_riple 3858d 10h /bustap-jtag/
20 Added support for 32bit Address bus. ash_riple 3858d 10h /bustap-jtag/
19 Minor changes. ash_riple 4272d 04h /bustap-jtag/
18 Added support for Xilinx Chips.
Added support for AXI4-Lite bus. Can be used as an XPS IP.		 ash_riple 4272d 05h /bustap-jtag/
17 Added unreachable trigger condition "@WR & @RD" checking. ash_riple 4518d 08h /bustap-jtag/
16 Released version 2.2. ash_riple 4540d 08h /bustap-jtag/
15 Released version 2.2. ash_riple 4540d 08h /bustap-jtag/
14 Changed dec to hex value of triggerPnum. ash_riple 4540d 23h /bustap-jtag/
13 Added minor syntax changes and Linux environment simulation script. ash_riple 4541d 04h /bustap-jtag/
12 Added timing information to the capture content. ash_riple 4541d 12h /bustap-jtag/
11 Added pre-trigger capture. ash_riple 4542d 04h /bustap-jtag/
10 Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure. ash_riple 4547d 09h /bustap-jtag/
9 Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do".
Virtual JTAG stimulus can only be entered statically before simulation starts.
FIFO operation can be simulated dynamically while simulation is run.		 ash_riple 4548d 04h /bustap-jtag/
8 Added fault handling of wrong input length in the GUI. ash_riple 4552d 03h /bustap-jtag/
7 Added references related to "Bus Monitor". ash_riple 4552d 08h /bustap-jtag/
6 Updated to 2.1. New features added as in doc/Revision History.txt. ash_riple 4553d 04h /bustap-jtag/
5 Created code base for 2.x development.
Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.		 ash_riple 4556d 05h /bustap-jtag/
4 Created tag for original source code. Version 1.0. ash_riple 4556d 07h /bustap-jtag/

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