URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] - Rev 21

Rev	Log message	Author	Age	Path
20	Added support for 32bit Address bus.	ash_riple	3789d 01h	/bustap-jtag/trunk/rtl/
18	Added support for Xilinx Chips. Added support for AXI4-Lite bus. Can be used as an XPS IP.	ash_riple	4202d 20h	/bustap-jtag/trunk/rtl/
15	Released version 2.2.	ash_riple	4470d 23h	/bustap-jtag/trunk/rtl/
13	Added minor syntax changes and Linux environment simulation script.	ash_riple	4471d 19h	/bustap-jtag/trunk/rtl/
12	Added timing information to the capture content.	ash_riple	4472d 03h	/bustap-jtag/trunk/rtl/
11	Added pre-trigger capture.	ash_riple	4472d 19h	/bustap-jtag/trunk/rtl/
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4478d 00h	/bustap-jtag/trunk/rtl/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4478d 19h	/bustap-jtag/trunk/rtl/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4483d 19h	/bustap-jtag/trunk/rtl/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4486d 20h	/bustap-jtag/trunk/rtl/
2	Checked in working code base.	ash_riple	4490d 19h	/bustap-jtag/trunk/rtl/