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[/] [bustap-jtag/] [trunk/] [rtl/] - Rev 21

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Rev Log message Author Age Path
20 Added support for 32bit Address bus. ash_riple 3791d 06h /bustap-jtag/trunk/rtl/
18 Added support for Xilinx Chips.
Added support for AXI4-Lite bus. Can be used as an XPS IP.
ash_riple 4205d 01h /bustap-jtag/trunk/rtl/
15 Released version 2.2. ash_riple 4473d 05h /bustap-jtag/trunk/rtl/
13 Added minor syntax changes and Linux environment simulation script. ash_riple 4474d 01h /bustap-jtag/trunk/rtl/
12 Added timing information to the capture content. ash_riple 4474d 09h /bustap-jtag/trunk/rtl/
11 Added pre-trigger capture. ash_riple 4475d 00h /bustap-jtag/trunk/rtl/
10 Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure. ash_riple 4480d 05h /bustap-jtag/trunk/rtl/
9 Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do".
Virtual JTAG stimulus can only be entered statically before simulation starts.
FIFO operation can be simulated dynamically while simulation is run.
ash_riple 4481d 00h /bustap-jtag/trunk/rtl/
6 Updated to 2.1. New features added as in doc/Revision History.txt. ash_riple 4486d 00h /bustap-jtag/trunk/rtl/
5 Created code base for 2.x development.
Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.
ash_riple 4489d 01h /bustap-jtag/trunk/rtl/
2 Checked in working code base. ash_riple 4493d 00h /bustap-jtag/trunk/rtl/

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