URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [altera/] - Rev 24

Rev	Log message	Author	Age	Path
24	Added support for Qsys based avalon transaction monitoring.	ash_riple	3574d 00h	/bustap-jtag/trunk/rtl/altera/
15	Released version 2.2.	ash_riple	4463d 04h	/bustap-jtag/trunk/rtl/altera/
11	Added pre-trigger capture.	ash_riple	4464d 23h	/bustap-jtag/trunk/rtl/altera/
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4470d 04h	/bustap-jtag/trunk/rtl/altera/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4470d 23h	/bustap-jtag/trunk/rtl/altera/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4475d 23h	/bustap-jtag/trunk/rtl/altera/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4479d 00h	/bustap-jtag/trunk/rtl/altera/
2	Checked in working code base.	ash_riple	4482d 23h	/bustap-jtag/trunk/rtl/altera/