URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [altera/] - Rev 13

Rev	Log message	Author	Age	Path
11	Added pre-trigger capture.	ash_riple	4471d 08h	/bustap-jtag/trunk/rtl/altera/
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4476d 13h	/bustap-jtag/trunk/rtl/altera/
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4477d 08h	/bustap-jtag/trunk/rtl/altera/
6	Updated to 2.1. New features added as in doc/Revision History.txt.	ash_riple	4482d 08h	/bustap-jtag/trunk/rtl/altera/
5	Created code base for 2.x development. Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.	ash_riple	4485d 09h	/bustap-jtag/trunk/rtl/altera/
2	Checked in working code base.	ash_riple	4489d 08h	/bustap-jtag/trunk/rtl/altera/