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Subversion Repositories c16

[/] [c16/] [trunk/] - Rev 23

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Rev	Log message	Author	Age	Path
23	Fixed problem with wishbone wait-states	jsauermann	6967d 14h	/c16/trunk/
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	6967d 19h	/c16/trunk/
19	FPGA Pin desription added.	jsauermann	7163d 16h	/c16/trunk/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7464d 15h	/c16/trunk/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7464d 15h	/c16/trunk/
16	Enable interrupts at start of each task. This fix is required after a change in opcode_decoder.vhd.	jsauermann	7464d 15h	/c16/trunk/
15	sample ucf file	jsauermann	7503d 18h	/c16/trunk/
14	no message	jsauermann	7511d 19h	/c16/trunk/
13	bug in print_unsigned() fixed. Now done as in rtos.c	jsauermann	7554d 12h	/c16/trunk/
12	Todo removed	jsauermann	7583d 10h	/c16/trunk/
11	First Version	jsauermann	7583d 10h	/c16/trunk/
10	Set top of stack of idle task to end of internal memory rather than end of external memory (causing incorrect display of 100 % CPU load).	jsauermann	7583d 12h	/c16/trunk/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7583d 12h	/c16/trunk/
8	Initialization of compound auto variables added (was TODO)	jsauermann	7590d 15h	/c16/trunk/
7	Handle auto variable declarations in compound statements properly	jsauermann	7591d 14h	/c16/trunk/
6	New Target polled for testing compiler without the need to simulate interrupts	jsauermann	7591d 15h	/c16/trunk/
5	Initial version	jsauermann	7592d 12h	/c16/trunk/
4	Documentation finalized	jsauermann	7592d 16h	/c16/trunk/
2	no message	jsauermann	7595d 11h	/c16/trunk/
1	Standard project directories initialized by cvs2svn.		7595d 11h	/c16/trunk/

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Subversion Repositories c16

[/] [c16/] [trunk/] - Rev 23

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