URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] [c16/] [trunk/] - Rev 26

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Rev	Log message	Author	Age	Path
26	New directory structure.	root	5718d 00h	/c16/trunk/
25	XOR bug fixed	jsauermann	6776d 07h	/trunk/
24	no message	jsauermann	6937d 05h	/trunk/
23	Fixed problem with wishbone wait-states	jsauermann	7077d 04h	/trunk/
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	7077d 09h	/trunk/
19	FPGA Pin desription added.	jsauermann	7273d 06h	/trunk/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7574d 05h	/trunk/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7574d 05h	/trunk/
16	Enable interrupts at start of each task. This fix is required after a change in opcode_decoder.vhd.	jsauermann	7574d 05h	/trunk/
15	sample ucf file	jsauermann	7613d 08h	/trunk/
14	no message	jsauermann	7621d 09h	/trunk/
13	bug in print_unsigned() fixed. Now done as in rtos.c	jsauermann	7664d 03h	/trunk/
12	Todo removed	jsauermann	7693d 01h	/trunk/
11	First Version	jsauermann	7693d 01h	/trunk/
10	Set top of stack of idle task to end of internal memory rather than end of external memory (causing incorrect display of 100 % CPU load).	jsauermann	7693d 02h	/trunk/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7693d 03h	/trunk/
8	Initialization of compound auto variables added (was TODO)	jsauermann	7700d 05h	/trunk/
7	Handle auto variable declarations in compound statements properly	jsauermann	7701d 05h	/trunk/
6	New Target polled for testing compiler without the need to simulate interrupts	jsauermann	7701d 05h	/trunk/
5	Initial version	jsauermann	7702d 02h	/trunk/

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Subversion Repositories c16

[/] [c16/] [trunk/] - Rev 26

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