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Rev Log message Author Age Path
29 fixed problems reported by buaa.byl jsauermann 4317d 21h /c16/trunk/
26 New directory structure. root 5562d 17h /c16/trunk/
25 XOR bug fixed jsauermann 6621d 00h /trunk/
24 no message jsauermann 6781d 22h /trunk/
23 Fixed problem with wishbone wait-states jsauermann 6921d 21h /trunk/
21 Changes for Xilinx Proj. Nav. 7.1.02i jsauermann 6922d 02h /trunk/
19 FPGA Pin desription added. jsauermann 7117d 23h /trunk/
18 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well
jsauermann 7418d 22h /trunk/
17 Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires a fix in rtos.c as well
jsauermann 7418d 22h /trunk/
16 Enable interrupts at start of each task.
This fix is required after a change in opcode_decoder.vhd.
jsauermann 7418d 22h /trunk/
15 sample ucf file jsauermann 7458d 01h /trunk/
14 no message jsauermann 7466d 02h /trunk/
13 bug in print_unsigned() fixed.
Now done as in rtos.c
jsauermann 7508d 20h /trunk/
12 Todo removed jsauermann 7537d 18h /trunk/
11 First Version jsauermann 7537d 18h /trunk/
10 Set top of stack of idle task to end of internal memory rather
than end of external memory (causing incorrect display of
100 % CPU load).
jsauermann 7537d 19h /trunk/
9 Made cpu_engine WISHBONE compliant.
(Somebody please validate it).
jsauermann 7537d 20h /trunk/
8 Initialization of compound auto variables added (was TODO) jsauermann 7544d 22h /trunk/
7 Handle auto variable declarations in compound statements properly jsauermann 7545d 22h /trunk/
6 New Target polled for testing compiler without the need to simulate interrupts jsauermann 7545d 22h /trunk/

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