URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] [c16/] [trunk/] [vhdl/] - Rev 21

Rev	Log message	Author	Age	Path
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	6967d 19h	/c16/trunk/vhdl/
19	FPGA Pin desription added.	jsauermann	7163d 16h	/c16/trunk/vhdl/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7464d 15h	/c16/trunk/vhdl/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7464d 15h	/c16/trunk/vhdl/
15	sample ucf file	jsauermann	7503d 18h	/c16/trunk/vhdl/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7583d 12h	/c16/trunk/vhdl/
7	Handle auto variable declarations in compound statements properly	jsauermann	7591d 15h	/c16/trunk/vhdl/
2	no message	jsauermann	7595d 11h	/c16/trunk/vhdl/