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[/] [can/] [tags/] [asyst_3/] - Rev 65

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Rev	Log message	Author	Age	Path
65	unix.	mohor	7789d 05h	/can/tags/asyst_3/
64	* empty log message *	mohor	7789d 05h	/can/tags/asyst_3/
63	ALE changes on negedge of clk.	mohor	7795d 03h	/can/tags/asyst_3/
62	can_cs signal used for generation of the cs.	mohor	7795d 03h	/can/tags/asyst_3/
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7797d 16h	/can/tags/asyst_3/
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7797d 17h	/can/tags/asyst_3/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7797d 18h	/can/tags/asyst_3/
58	timescale.v is used for simulation only.	mohor	7798d 06h	/can/tags/asyst_3/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7798d 06h	/can/tags/asyst_3/
56	Doubled declarations removed.	mohor	7799d 05h	/can/tags/asyst_3/
55	wire declaration added.	mohor	7799d 05h	/can/tags/asyst_3/
53	CAN pins located.	mohor	7804d 07h	/can/tags/asyst_3/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7804d 07h	/can/tags/asyst_3/
51	Xilinx RAM added.	mohor	7804d 07h	/can/tags/asyst_3/
50	Top level signal names changed.	mohor	7804d 07h	/can/tags/asyst_3/
49	Actel APA ram changed. Now synchronous read is used.	mohor	7807d 23h	/can/tags/asyst_3/
48	Actel APA ram supported.	mohor	7807d 23h	/can/tags/asyst_3/
47	Data is latched on read.	mohor	7807d 23h	/can/tags/asyst_3/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7817d 22h	/can/tags/asyst_3/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7817d 23h	/can/tags/asyst_3/

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[/] [can/] [tags/] [asyst_3/] - Rev 65

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