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Rev Log message Author Age Path
51 Xilinx RAM added. mohor 7804d 04h /can/tags/rel_11/
50 Top level signal names changed. mohor 7804d 04h /can/tags/rel_11/
49 Actel APA ram changed. Now synchronous read is used. mohor 7807d 20h /can/tags/rel_11/
48 Actel APA ram supported. mohor 7807d 20h /can/tags/rel_11/
47 Data is latched on read. mohor 7807d 20h /can/tags/rel_11/
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.		 mohor 7817d 19h /can/tags/rel_11/
44 When bit error occured while active error flag was transmitted, counter was
not incremented.		 mohor 7817d 20h /can/tags/rel_11/
43 Directory keeper. mohor 7818d 02h /can/tags/rel_11/
42 Initial version of the project. mohor 7818d 02h /can/tags/rel_11/
41 Incomplete sensitivity list fixed. mohor 7818d 04h /can/tags/rel_11/
40 Typo fixed. mohor 7818d 04h /can/tags/rel_11/
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7818d 04h /can/tags/rel_11/
38 Temporary backup version (still fully operable). mohor 7819d 19h /can/tags/rel_11/
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7819d 19h /can/tags/rel_11/
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.		 mohor 7819d 19h /can/tags/rel_11/
35 Several registers added. Not finished, yet. mohor 7822d 23h /can/tags/rel_11/
34 Errors monitoring improved. arbitration_lost improved. mohor 7825d 05h /can/tags/rel_11/
33 abort_tx added. mohor 7825d 05h /can/tags/rel_11/
32 abort_tx added. Bit destuff fixed. mohor 7825d 05h /can/tags/rel_11/
31 Wishbone interface added. mohor 7826d 18h /can/tags/rel_11/

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