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[/] [can/] [tags/] [rel_12/] - Rev 70

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Rev	Log message	Author	Age	Path
70	data_out is already registered in the can_top.v file.	mohor	7708d 08h	/can/tags/rel_12/
69	Some features are supported in extended mode only (listen_only_mode...).	mohor	7763d 04h	/can/tags/rel_12/
68	CAN inturrupt is active low.	mohor	7783d 08h	/can/tags/rel_12/
67	CAN interrupt is active low.	mohor	7783d 08h	/can/tags/rel_12/
66	unix.	mohor	7789d 03h	/can/tags/rel_12/
65	unix.	mohor	7789d 03h	/can/tags/rel_12/
64	* empty log message *	mohor	7789d 03h	/can/tags/rel_12/
63	ALE changes on negedge of clk.	mohor	7795d 00h	/can/tags/rel_12/
62	can_cs signal used for generation of the cs.	mohor	7795d 00h	/can/tags/rel_12/
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7797d 14h	/can/tags/rel_12/
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7797d 15h	/can/tags/rel_12/
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7797d 15h	/can/tags/rel_12/
58	timescale.v is used for simulation only.	mohor	7798d 03h	/can/tags/rel_12/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7798d 03h	/can/tags/rel_12/
56	Doubled declarations removed.	mohor	7799d 02h	/can/tags/rel_12/
55	wire declaration added.	mohor	7799d 02h	/can/tags/rel_12/
53	CAN pins located.	mohor	7804d 04h	/can/tags/rel_12/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7804d 04h	/can/tags/rel_12/
51	Xilinx RAM added.	mohor	7804d 05h	/can/tags/rel_12/
50	Top level signal names changed.	mohor	7804d 05h	/can/tags/rel_12/

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[/] [can/] [tags/] [rel_12/] - Rev 70

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