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[/] [can/] [tags/] [rel_12/] [bench/] [verilog/] - Rev 52

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Rev	Log message	Author	Age	Path
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7835d 04h	/can/tags/rel_12/bench/verilog/
50	Top level signal names changed.	mohor	7835d 04h	/can/tags/rel_12/bench/verilog/
48	Actel APA ram supported.	mohor	7838d 20h	/can/tags/rel_12/bench/verilog/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7849d 05h	/can/tags/rel_12/bench/verilog/
38	Temporary backup version (still fully operable).	mohor	7850d 19h	/can/tags/rel_12/bench/verilog/
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7850d 19h	/can/tags/rel_12/bench/verilog/
35	Several registers added. Not finished, yet.	mohor	7853d 23h	/can/tags/rel_12/bench/verilog/
34	Errors monitoring improved. arbitration_lost improved.	mohor	7856d 05h	/can/tags/rel_12/bench/verilog/
31	Wishbone interface added.	mohor	7857d 18h	/can/tags/rel_12/bench/verilog/
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7859d 01h	/can/tags/rel_12/bench/verilog/
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7859d 17h	/can/tags/rel_12/bench/verilog/
26	Backup.	mohor	7864d 02h	/can/tags/rel_12/bench/verilog/
25	* empty log message *	mohor	7864d 05h	/can/tags/rel_12/bench/verilog/
24	backup.	mohor	7868d 18h	/can/tags/rel_12/bench/verilog/
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7883d 06h	/can/tags/rel_12/bench/verilog/
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7883d 22h	/can/tags/rel_12/bench/verilog/
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7884d 05h	/can/tags/rel_12/bench/verilog/
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7884d 06h	/can/tags/rel_12/bench/verilog/
17	Addresses corrected to decimal values (previously hex).	mohor	7885d 02h	/can/tags/rel_12/bench/verilog/
16	rx_fifo is now working.	mohor	7885d 07h	/can/tags/rel_12/bench/verilog/

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