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[/] [can/] [tags/] [rel_12/] [rtl/] - Rev 59

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Rev	Log message	Author	Age	Path
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7797d 14h	/can/tags/rel_12/rtl/
58	timescale.v is used for simulation only.	mohor	7798d 02h	/can/tags/rel_12/rtl/
57	Mux used for clkout to avoid "gated clocks warning".	mohor	7798d 02h	/can/tags/rel_12/rtl/
56	Doubled declarations removed.	mohor	7799d 01h	/can/tags/rel_12/rtl/
55	wire declaration added.	mohor	7799d 01h	/can/tags/rel_12/rtl/
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7804d 03h	/can/tags/rel_12/rtl/
51	Xilinx RAM added.	mohor	7804d 03h	/can/tags/rel_12/rtl/
50	Top level signal names changed.	mohor	7804d 03h	/can/tags/rel_12/rtl/
48	Actel APA ram supported.	mohor	7807d 20h	/can/tags/rel_12/rtl/
47	Data is latched on read.	mohor	7807d 20h	/can/tags/rel_12/rtl/
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7817d 18h	/can/tags/rel_12/rtl/
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7817d 19h	/can/tags/rel_12/rtl/
41	Incomplete sensitivity list fixed.	mohor	7818d 03h	/can/tags/rel_12/rtl/
40	Typo fixed.	mohor	7818d 03h	/can/tags/rel_12/rtl/
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7818d 04h	/can/tags/rel_12/rtl/
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7819d 18h	/can/tags/rel_12/rtl/
35	Several registers added. Not finished, yet.	mohor	7822d 22h	/can/tags/rel_12/rtl/
33	abort_tx added.	mohor	7825d 04h	/can/tags/rel_12/rtl/
32	abort_tx added. Bit destuff fixed.	mohor	7825d 04h	/can/tags/rel_12/rtl/
31	Wishbone interface added.	mohor	7826d 18h	/can/tags/rel_12/rtl/

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[/] [can/] [tags/] [rel_12/] [rtl/] - Rev 59

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