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[/] [can/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 163

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5589d 11h	/can/tags/rel_12/rtl/verilog/
113	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7650d 16h	/can/tags/rel_12/rtl/verilog/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7650d 16h	/can/tags/rel_12/rtl/verilog/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7652d 16h	/can/tags/rel_12/rtl/verilog/
110	Fixed according to the linter.	mohor	7652d 16h	/can/tags/rel_12/rtl/verilog/
109	Fixed according to the linter.	mohor	7652d 17h	/can/tags/rel_12/rtl/verilog/
108	Fixed according to the linter.	mohor	7652d 17h	/can/tags/rel_12/rtl/verilog/
107	Fixed according to the linter.	mohor	7652d 18h	/can/tags/rel_12/rtl/verilog/
106	Unused signal removed.	mohor	7658d 16h	/can/tags/rel_12/rtl/verilog/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7659d 05h	/can/tags/rel_12/rtl/verilog/
102	Little fixes (to fix warnings).	mohor	7661d 20h	/can/tags/rel_12/rtl/verilog/
100	Synchronization changed.	mohor	7665d 22h	/can/tags/rel_12/rtl/verilog/
99	PCI_BIST replaced with CAN_BIST.	mohor	7665d 22h	/can/tags/rel_12/rtl/verilog/
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7671d 09h	/can/tags/rel_12/rtl/verilog/
95	Virtual silicon ram instances added.	simons	7671d 10h	/can/tags/rel_12/rtl/verilog/
93	synthesis full_case parallel_case fixed.	mohor	7676d 21h	/can/tags/rel_12/rtl/verilog/
92	clkout is clk/2 after the reset.	mohor	7677d 06h	/can/tags/rel_12/rtl/verilog/
90	paralel_case and full_case compiler directives added to case statements.	mohor	7677d 19h	/can/tags/rel_12/rtl/verilog/
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7678d 16h	/can/tags/rel_12/rtl/verilog/
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7678d 17h	/can/tags/rel_12/rtl/verilog/

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[/] [can/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 163

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