OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 79

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7730d 19h /can/tags/rel_12/rtl/verilog/
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.
mohor 7730d 19h /can/tags/rel_12/rtl/verilog/
77 Synchronization is also needed when transmitting a message. mohor 7733d 18h /can/tags/rel_12/rtl/verilog/
76 Counters width changed. mohor 7733d 18h /can/tags/rel_12/rtl/verilog/
75 When switching to tx, sync stage is overjumped. mohor 7735d 19h /can/tags/rel_12/rtl/verilog/
73 overrun and length_info fifos are initialized at the end of reset. mohor 7736d 00h /can/tags/rel_12/rtl/verilog/
71 Ports added for the CAN_BIST. mohor 7737d 22h /can/tags/rel_12/rtl/verilog/
70 data_out is already registered in the can_top.v file. mohor 7737d 22h /can/tags/rel_12/rtl/verilog/
69 Some features are supported in extended mode only (listen_only_mode...). mohor 7792d 18h /can/tags/rel_12/rtl/verilog/
67 CAN interrupt is active low. mohor 7812d 22h /can/tags/rel_12/rtl/verilog/
66 unix. mohor 7818d 16h /can/tags/rel_12/rtl/verilog/
65 unix. mohor 7818d 16h /can/tags/rel_12/rtl/verilog/
64 *** empty log message *** mohor 7818d 16h /can/tags/rel_12/rtl/verilog/
62 can_cs signal used for generation of the cs. mohor 7824d 14h /can/tags/rel_12/rtl/verilog/
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.
mohor 7827d 03h /can/tags/rel_12/rtl/verilog/
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.
mohor 7827d 05h /can/tags/rel_12/rtl/verilog/
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.
mohor 7827d 05h /can/tags/rel_12/rtl/verilog/
58 timescale.v is used for simulation only. mohor 7827d 17h /can/tags/rel_12/rtl/verilog/
57 Mux used for clkout to avoid "gated clocks warning". mohor 7827d 17h /can/tags/rel_12/rtl/verilog/
56 Doubled declarations removed. mohor 7828d 16h /can/tags/rel_12/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.