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[/] [can/] [tags/] [rel_12/] [sim/] [rtl_sim/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5563d 15h /can/tags/rel_12/sim/rtl_sim/
113 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7624d 20h /can/tags/rel_12/sim/rtl_sim/
48 Actel APA ram supported. mohor 7763d 12h /can/tags/rel_12/sim/rtl_sim/
35 Several registers added. Not finished, yet. mohor 7778d 15h /can/tags/rel_12/sim/rtl_sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7783d 17h /can/tags/rel_12/sim/rtl_sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7784d 09h /can/tags/rel_12/sim/rtl_sim/
25 *** empty log message *** mohor 7788d 21h /can/tags/rel_12/sim/rtl_sim/
24 backup. mohor 7793d 10h /can/tags/rel_12/sim/rtl_sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7808d 22h /can/tags/rel_12/sim/rtl_sim/
16 rx_fifo is now working. mohor 7809d 23h /can/tags/rel_12/sim/rtl_sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7814d 13h /can/tags/rel_12/sim/rtl_sim/
13 Temporary files (backup). mohor 7814d 20h /can/tags/rel_12/sim/rtl_sim/
11 Acceptance filter added. mohor 7816d 09h /can/tags/rel_12/sim/rtl_sim/
8 Testbench define file added. Clock divider register added. mohor 7828d 19h /can/tags/rel_12/sim/rtl_sim/
5 Synchronization working. mohor 7829d 21h /can/tags/rel_12/sim/rtl_sim/
4 Dir keeper. mohor 7834d 18h /can/tags/rel_12/sim/rtl_sim/
2 Initial mohor 7834d 19h /can/tags/rel_12/sim/rtl_sim/

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