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Rev Log message Author Age Path
161 New directory structure. root 5623d 03h /can/tags/rel_12/sim/rtl_sim/
113 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7684d 08h /can/tags/rel_12/sim/rtl_sim/
48 Actel APA ram supported. mohor 7823d 00h /can/tags/rel_12/sim/rtl_sim/
35 Several registers added. Not finished, yet. mohor 7838d 03h /can/tags/rel_12/sim/rtl_sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7843d 04h /can/tags/rel_12/sim/rtl_sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7843d 21h /can/tags/rel_12/sim/rtl_sim/
25 *** empty log message *** mohor 7848d 09h /can/tags/rel_12/sim/rtl_sim/
24 backup. mohor 7852d 22h /can/tags/rel_12/sim/rtl_sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7868d 10h /can/tags/rel_12/sim/rtl_sim/
16 rx_fifo is now working. mohor 7869d 11h /can/tags/rel_12/sim/rtl_sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7874d 01h /can/tags/rel_12/sim/rtl_sim/
13 Temporary files (backup). mohor 7874d 08h /can/tags/rel_12/sim/rtl_sim/
11 Acceptance filter added. mohor 7875d 21h /can/tags/rel_12/sim/rtl_sim/
8 Testbench define file added. Clock divider register added. mohor 7888d 07h /can/tags/rel_12/sim/rtl_sim/
5 Synchronization working. mohor 7889d 09h /can/tags/rel_12/sim/rtl_sim/
4 Dir keeper. mohor 7894d 06h /can/tags/rel_12/sim/rtl_sim/
2 Initial mohor 7894d 06h /can/tags/rel_12/sim/rtl_sim/

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