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[/] [can/] [tags/] [rel_14/] [sim/] [rtl_sim/] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5571d 12h /can/tags/rel_14/sim/rtl_sim/
116 This commit was manufactured by cvs2svn to create tag 'rel_14'. 7605d 16h /can/tags/rel_14/sim/rtl_sim/
48 Actel APA ram supported. mohor 7771d 09h /can/tags/rel_14/sim/rtl_sim/
35 Several registers added. Not finished, yet. mohor 7786d 12h /can/tags/rel_14/sim/rtl_sim/
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7791d 13h /can/tags/rel_14/sim/rtl_sim/
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7792d 06h /can/tags/rel_14/sim/rtl_sim/
25 *** empty log message *** mohor 7796d 17h /can/tags/rel_14/sim/rtl_sim/
24 backup. mohor 7801d 07h /can/tags/rel_14/sim/rtl_sim/
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7816d 19h /can/tags/rel_14/sim/rtl_sim/
16 rx_fifo is now working. mohor 7817d 20h /can/tags/rel_14/sim/rtl_sim/
14 rx fifo added. Not 100 % verified, yet. mohor 7822d 10h /can/tags/rel_14/sim/rtl_sim/
13 Temporary files (backup). mohor 7822d 17h /can/tags/rel_14/sim/rtl_sim/
11 Acceptance filter added. mohor 7824d 06h /can/tags/rel_14/sim/rtl_sim/
8 Testbench define file added. Clock divider register added. mohor 7836d 16h /can/tags/rel_14/sim/rtl_sim/
5 Synchronization working. mohor 7837d 18h /can/tags/rel_14/sim/rtl_sim/
4 Dir keeper. mohor 7842d 15h /can/tags/rel_14/sim/rtl_sim/
2 Initial mohor 7842d 15h /can/tags/rel_14/sim/rtl_sim/

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