OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] - Rev 161

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
161 New directory structure. root 5591d 19h /can/tags/rel_16/rtl/verilog/
122 This commit was manufactured by cvs2svn to create tag 'rel_16'. 7611d 08h /can/tags/rel_16/rtl/verilog/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7611d 08h /can/tags/rel_16/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7620d 05h /can/tags/rel_16/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7620d 05h /can/tags/rel_16/rtl/verilog/
115 Artisan ram instances added. simons 7625d 23h /can/tags/rel_16/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7653d 00h /can/tags/rel_16/rtl/verilog/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7655d 00h /can/tags/rel_16/rtl/verilog/
110 Fixed according to the linter. mohor 7655d 00h /can/tags/rel_16/rtl/verilog/
109 Fixed according to the linter. mohor 7655d 01h /can/tags/rel_16/rtl/verilog/
108 Fixed according to the linter. mohor 7655d 01h /can/tags/rel_16/rtl/verilog/
107 Fixed according to the linter. mohor 7655d 02h /can/tags/rel_16/rtl/verilog/
106 Unused signal removed. mohor 7661d 00h /can/tags/rel_16/rtl/verilog/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7661d 13h /can/tags/rel_16/rtl/verilog/
102 Little fixes (to fix warnings). mohor 7664d 04h /can/tags/rel_16/rtl/verilog/
100 Synchronization changed. mohor 7668d 06h /can/tags/rel_16/rtl/verilog/
99 PCI_BIST replaced with CAN_BIST. mohor 7668d 06h /can/tags/rel_16/rtl/verilog/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7673d 17h /can/tags/rel_16/rtl/verilog/
95 Virtual silicon ram instances added. simons 7673d 18h /can/tags/rel_16/rtl/verilog/
93 synthesis full_case parallel_case fixed. mohor 7679d 05h /can/tags/rel_16/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.