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[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] - Rev 121

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Rev Log message Author Age Path
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7611d 12h /can/tags/rel_16/rtl/verilog/
118 Artisan RAM fixed (when not using BIST). mohor 7620d 09h /can/tags/rel_16/rtl/verilog/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7620d 09h /can/tags/rel_16/rtl/verilog/
115 Artisan ram instances added. simons 7626d 03h /can/tags/rel_16/rtl/verilog/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7653d 03h /can/tags/rel_16/rtl/verilog/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7655d 03h /can/tags/rel_16/rtl/verilog/
110 Fixed according to the linter. mohor 7655d 04h /can/tags/rel_16/rtl/verilog/
109 Fixed according to the linter. mohor 7655d 05h /can/tags/rel_16/rtl/verilog/
108 Fixed according to the linter. mohor 7655d 05h /can/tags/rel_16/rtl/verilog/
107 Fixed according to the linter. mohor 7655d 06h /can/tags/rel_16/rtl/verilog/
106 Unused signal removed. mohor 7661d 03h /can/tags/rel_16/rtl/verilog/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7661d 17h /can/tags/rel_16/rtl/verilog/
102 Little fixes (to fix warnings). mohor 7664d 07h /can/tags/rel_16/rtl/verilog/
100 Synchronization changed. mohor 7668d 09h /can/tags/rel_16/rtl/verilog/
99 PCI_BIST replaced with CAN_BIST. mohor 7668d 09h /can/tags/rel_16/rtl/verilog/
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7673d 21h /can/tags/rel_16/rtl/verilog/
95 Virtual silicon ram instances added. simons 7673d 22h /can/tags/rel_16/rtl/verilog/
93 synthesis full_case parallel_case fixed. mohor 7679d 09h /can/tags/rel_16/rtl/verilog/
92 clkout is clk/2 after the reset. mohor 7679d 17h /can/tags/rel_16/rtl/verilog/
90 paralel_case and full_case compiler directives added to case statements. mohor 7680d 07h /can/tags/rel_16/rtl/verilog/

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