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Rev	Log message	Author	Age	Path
122	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7723d 06h	/can/tags/rel_16/rtl/verilog/
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7723d 06h	/can/tags/rel_16/rtl/verilog/
118	Artisan RAM fixed (when not using BIST).	mohor	7732d 03h	/can/tags/rel_16/rtl/verilog/
117	Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need to be joined together on higher level.	mohor	7732d 03h	/can/tags/rel_16/rtl/verilog/
115	Artisan ram instances added.	simons	7737d 21h	/can/tags/rel_16/rtl/verilog/
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7764d 21h	/can/tags/rel_16/rtl/verilog/
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7766d 21h	/can/tags/rel_16/rtl/verilog/
110	Fixed according to the linter.	mohor	7766d 21h	/can/tags/rel_16/rtl/verilog/
109	Fixed according to the linter.	mohor	7766d 23h	/can/tags/rel_16/rtl/verilog/
108	Fixed according to the linter.	mohor	7766d 23h	/can/tags/rel_16/rtl/verilog/
107	Fixed according to the linter.	mohor	7766d 23h	/can/tags/rel_16/rtl/verilog/
106	Unused signal removed.	mohor	7772d 21h	/can/tags/rel_16/rtl/verilog/
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7773d 11h	/can/tags/rel_16/rtl/verilog/
102	Little fixes (to fix warnings).	mohor	7776d 01h	/can/tags/rel_16/rtl/verilog/
100	Synchronization changed.	mohor	7780d 03h	/can/tags/rel_16/rtl/verilog/
99	PCI_BIST replaced with CAN_BIST.	mohor	7780d 03h	/can/tags/rel_16/rtl/verilog/
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7785d 14h	/can/tags/rel_16/rtl/verilog/
95	Virtual silicon ram instances added.	simons	7785d 16h	/can/tags/rel_16/rtl/verilog/
93	synthesis full_case parallel_case fixed.	mohor	7791d 03h	/can/tags/rel_16/rtl/verilog/
92	clkout is clk/2 after the reset.	mohor	7791d 11h	/can/tags/rel_16/rtl/verilog/

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[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] - Rev 122

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